As is known, in applications at high frequency (for example, between some hundreds of MHz and some GHz) and high power, where the individual MOS devices supply powers comprised between fractions of a watt and some hundreds of watts, it is convenient to operate with supply voltages that may exceed 30 V. More in general, it is convenient, as the power requirement increases, to increase the voltage range across the device during operation. This range is limited by the drain-to-source breakdown voltage (Bvdss). For example, in amplifiers that operate in “class A” or “class B”, the “instantaneous” drain-to-source voltage of the power MOS device may reach values that are twice that of the supply voltage. This implies that the drain-to-source breakdown voltage of the device must be in the region of 70 V, which may impose dimensional constraints on some important regions of the device.
Said constraints contrast, however, with the achievement of high dynamic performances. In fact, to achieve these performances may require the use of sub-micrometric gate lengths. These lengths are in fact commonly used for the same purpose in other technologies, such as, for example, CMOS technology, where, however, the above geometrical parameter is normally reduced at the expense of the supply voltage. A similar problem arises for the light-doped drain (LDD) region, which often is rendered longer, at the expense of the resistance that it offers to the passage of current, to withstand high voltages.
In addition to these contrasting requirements, operating at the high voltages referred to, well-known phenomena of electrical degradation, due to hot-carrier injection (HCI), may arise, which render it even more difficult to reach the compromise between the various requirements and which set a limit to the dynamic performance of the device.
In order to improve the dynamic performance, one may reduce the reaction capacitance Cgd between the gate and the drain of the device. In fact, by reducing this capacitance, it is possible to obtain an improvement in the figure of merit fmax (maximum oscillation frequency) or more in general in the power gain. In addition, the minimization of the variation in capacitance as the drain voltage varies reduces the intermodulation distortion generated by the device while amplifying a modulated signal. Since the power gain decreases as the operating frequency increases, a top limit is set to the frequency at which it is still convenient to use the device. In order to operate usefully at higher frequencies, it is then necessary to design the device so that it initially has a higher gain. Thereby, also at the maximum oscillation frequency fmax, it is able to operate with desired power gain.
Solutions are known to the art for reducing the intrinsic capacitive coupling between the gate electrode and the drain region and minimizing the hot-carrier phenomena, which, by causing charge trapping near the gate region, degrade the electrical performance of the device.
For example, the article “Novel LDMOS Structures for 2 GHz High Power Basestation Application” by H. F. F. Jos, 28th European Microwave Conference Proceedings, Amsterdam, NL, vol. 1, Oct. 6, 1998, which is incorporated by reference, describes a structure for reducing the gate-to-drain capacitance Cgd, which comprises a metal path referred to as “shield metal”, which is defined, with a lithographic process, simultaneously to the gate metal and to the drain metal. This solution sets constraints on the length of the drain-extension region, since the shield-metal region must be defined within this space. In addition, the known solution does enable reduction of the capacitance between the drain metal and the gate metal, but is far from effective in reducing the intrinsic capacitance between the polysilicon gate electrode and the drain-extension region, which contributes also to the total gate-to-drain capacitance Cgd.
WO 00/49663 and EP-A-1 635 399, which are incorporated by reference, describe the formation of shield regions of a conductive material deposited only on one side of the gate region, on top of the drain region, thereby enabling a drastic reduction in the capacitive coupling between the gate electrode and the drain region.
In both solutions, it is disadvantageous that, when the drain-extension region is slightly depleted and consequently the neutral drain region is close to the gate electrode, there is an increase in the gate-to-drain parasitic capacitance, which is worsened by the fact that the thickness of the gate oxide, which separates the two regions referred to above, is normally of some tens of nanometers.
In the known solutions, then, the drain region is found in the proximity of the channel region underneath the gate region, when the latter is biased. The voltage applied to the drain has a marked influence on the channel region and consequently modulates the current of the device, giving rise, should the gate length not be sufficient, to the well-known short-channel effects.